Debug trace of cache memory requests

An apparatus includes a plurality of processor circuits, a cache memory circuit, and a trace control circuit. The trace control circuit may be configured, in response to activation of a mode to record information indicative of program execution of at least one processor circuit of the plurality of p...

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Bibliographische Detailangaben

Hauptverfasser:	Potnuru, Krishna C, Gupta, Sandeep, Beaumont-Smith, Andrew J, Knoth, Matthias
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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