Four-phase twenty-five percent duty cycle clock generator

A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input...

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1. Verfasser:	Lin, Chia-Liang (Leon)
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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creator	Lin, Chia-Liang (Leon)
description	A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input clock; and two cross-coupling latches configured to provide cross-coupling between the first pair of gated amplifiers and the second pair of gated amplifiers.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11728793B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11728793B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11728793B13</originalsourceid><addsrcrecordid>eNrjZLB0yy8t0i3ISCxOVSgpT80rqdRNyyxLVShILUoG8hRSSksqFZIrk3NSFZJz8pOzFdJT81KLEkvyi3gYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQSJQf2pJfGiwoaG5kYW5pbGToTExagBZTC8U</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Four-phase twenty-five percent duty cycle clock generator</title><source>esp@cenet</source><creator>Lin, Chia-Liang (Leon)</creator><creatorcontrib>Lin, Chia-Liang (Leon)</creatorcontrib><description>A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input clock; and two cross-coupling latches configured to provide cross-coupling between the first pair of gated amplifiers and the second pair of gated amplifiers.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230815&DB=EPODOC&CC=US&NR=11728793B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230815&DB=EPODOC&CC=US&NR=11728793B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lin, Chia-Liang (Leon)</creatorcontrib><title>Four-phase twenty-five percent duty cycle clock generator</title><description>A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input clock; and two cross-coupling latches configured to provide cross-coupling between the first pair of gated amplifiers and the second pair of gated amplifiers.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB0yy8t0i3ISCxOVSgpT80rqdRNyyxLVShILUoG8hRSSksqFZIrk3NSFZJz8pOzFdJT81KLEkvyi3gYWNMSc4pTeaE0N4Oim2uIs4duakF-fGpxQSJQf2pJfGiwoaG5kYW5pbGToTExagBZTC8U</recordid><startdate>20230815</startdate><enddate>20230815</enddate><creator>Lin, Chia-Liang (Leon)</creator><scope>EVB</scope></search><sort><creationdate>20230815</creationdate><title>Four-phase twenty-five percent duty cycle clock generator</title><author>Lin, Chia-Liang (Leon)</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11728793B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>Lin, Chia-Liang (Leon)</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lin, Chia-Liang (Leon)</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Four-phase twenty-five percent duty cycle clock generator</title><date>2023-08-15</date><risdate>2023</risdate><abstract>A four-stage gated ring oscillator having four gated amplifiers configured in a ring topology and comprising a first pair of gated amplifiers, controlled by a first phase of an two-phase input clock, interleaved with a second pair gated amplifiers, controlled by a second phase of the two-phase input clock; and two cross-coupling latches configured to provide cross-coupling between the first pair of gated amplifiers and the second pair of gated amplifiers.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
title	Four-phase twenty-five percent duty cycle clock generator
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