Integrated circuit device and method of manufacturing the same

An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of n...

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Hauptverfasser: Bae, Dong-il, Son, Nak-jin
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creator Bae, Dong-il
Son, Nak-jin
description An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11715786B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11715786B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11715786B23</originalsourceid><addsrcrecordid>eNrjZLDzzCtJTS9KLElNUUjOLEouzSxRSEkty0xOVUjMS1HITS3JyE9RyE9TyE3MK01LTC4pLcrMS1coyUhVKE7MTeVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaG5oam5hZmTkbGxKgBAFhGMK8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit device and method of manufacturing the same</title><source>esp@cenet</source><creator>Bae, Dong-il ; Son, Nak-jin</creator><creatorcontrib>Bae, Dong-il ; Son, Nak-jin</creatorcontrib><description>An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES ; NANOTECHNOLOGY ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES ; TRANSPORTING</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230801&amp;DB=EPODOC&amp;CC=US&amp;NR=11715786B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230801&amp;DB=EPODOC&amp;CC=US&amp;NR=11715786B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Bae, Dong-il</creatorcontrib><creatorcontrib>Son, Nak-jin</creatorcontrib><title>Integrated circuit device and method of manufacturing the same</title><description>An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</subject><subject>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</subject><subject>NANOTECHNOLOGY</subject><subject>PERFORMING OPERATIONS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDzzCtJTS9KLElNUUjOLEouzSxRSEkty0xOVUjMS1HITS3JyE9RyE9TyE3MK01LTC4pLcrMS1coyUhVKE7MTeVhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaG5oam5hZmTkbGxKgBAFhGMK8</recordid><startdate>20230801</startdate><enddate>20230801</enddate><creator>Bae, Dong-il</creator><creator>Son, Nak-jin</creator><scope>EVB</scope></search><sort><creationdate>20230801</creationdate><title>Integrated circuit device and method of manufacturing the same</title><author>Bae, Dong-il ; Son, Nak-jin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11715786B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OR TREATMENT OF NANOSTRUCTURES</topic><topic>MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES</topic><topic>NANOTECHNOLOGY</topic><topic>PERFORMING OPERATIONS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>Bae, Dong-il</creatorcontrib><creatorcontrib>Son, Nak-jin</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bae, Dong-il</au><au>Son, Nak-jin</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit device and method of manufacturing the same</title><date>2023-08-01</date><risdate>2023</risdate><abstract>An integrated circuit device includes: a fin-type active area including a fin top surface on a top portion and an anti-punch-through recess having a lowermost level lower than a level of the fin top surface; a nanosheet stack facing the fin top surface, the nanosheet stack including a plurality of nanosheets having vertical distances different from each other from the fin top surface; a gate structure surrounding each of the plurality of nanosheets; a source/drain region having a side wall facing at least one of the plurality of nanosheets; and an anti-punch-through semiconductor layer including a first portion filling the anti-punch-through recess, and a second portion being in contact with a side wall of a first nanosheet most adjacent to the fin-type active area among the plurality of nanosheets, the anti-punch-through semiconductor layer including a material different from a material of the source/drain region.</abstract><oa>free_for_read</oa></addata></record>
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recordid cdi_epo_espacenet_US11715786B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES
NANOTECHNOLOGY
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES
TRANSPORTING
title Integrated circuit device and method of manufacturing the same
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-29T00%3A17%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Bae,%20Dong-il&rft.date=2023-08-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11715786B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true