Method for fabricating semiconductor package
A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicke...
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| creator | Park, Jung-Ho Lee, Seok Hyun Jang, Jae Gwon Park, Jin-Woo Jeon, Gwang Jae |
| description | A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11715645B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11715645B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11715645B23</originalsourceid><addsrcrecordid>eNrjZNDxTS3JyE9RSMsvUkhLTCrKTE4sycxLVyhOzc1Mzs9LKU0uAcoUJCZnJ6an8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41GKgqtS81JL40GBDQ3NDUzMTUycjY2LUAACuhSow</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for fabricating semiconductor package</title><source>esp@cenet</source><creator>Park, Jung-Ho ; Lee, Seok Hyun ; Jang, Jae Gwon ; Park, Jin-Woo ; Jeon, Gwang Jae</creator><creatorcontrib>Park, Jung-Ho ; Lee, Seok Hyun ; Jang, Jae Gwon ; Park, Jin-Woo ; Jeon, Gwang Jae</creatorcontrib><description>A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230801&DB=EPODOC&CC=US&NR=11715645B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230801&DB=EPODOC&CC=US&NR=11715645B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Park, Jung-Ho</creatorcontrib><creatorcontrib>Lee, Seok Hyun</creatorcontrib><creatorcontrib>Jang, Jae Gwon</creatorcontrib><creatorcontrib>Park, Jin-Woo</creatorcontrib><creatorcontrib>Jeon, Gwang Jae</creatorcontrib><title>Method for fabricating semiconductor package</title><description>A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNDxTS3JyE9RSMsvUkhLTCrKTE4sycxLVyhOzc1Mzs9LKU0uAcoUJCZnJ6an8jCwpiXmFKfyQmluBkU31xBnD93Ugvz41GKgqtS81JL40GBDQ3NDUzMTUycjY2LUAACuhSow</recordid><startdate>20230801</startdate><enddate>20230801</enddate><creator>Park, Jung-Ho</creator><creator>Lee, Seok Hyun</creator><creator>Jang, Jae Gwon</creator><creator>Park, Jin-Woo</creator><creator>Jeon, Gwang Jae</creator><scope>EVB</scope></search><sort><creationdate>20230801</creationdate><title>Method for fabricating semiconductor package</title><author>Park, Jung-Ho ; Lee, Seok Hyun ; Jang, Jae Gwon ; Park, Jin-Woo ; Jeon, Gwang Jae</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11715645B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Park, Jung-Ho</creatorcontrib><creatorcontrib>Lee, Seok Hyun</creatorcontrib><creatorcontrib>Jang, Jae Gwon</creatorcontrib><creatorcontrib>Park, Jin-Woo</creatorcontrib><creatorcontrib>Jeon, Gwang Jae</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Park, Jung-Ho</au><au>Lee, Seok Hyun</au><au>Jang, Jae Gwon</au><au>Park, Jin-Woo</au><au>Jeon, Gwang Jae</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for fabricating semiconductor package</title><date>2023-08-01</date><risdate>2023</risdate><abstract>A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.</abstract><oa>free_for_read</oa></addata></record> |
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| title | Method for fabricating semiconductor package |
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