Package structure and fabricating method thereof
A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is dis...
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creator | Hou, Shang-Yun Huang, Kuan-Yu Huang, Sung-Hui |
description | A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11705407B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11705407B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11705407B23</originalsourceid><addsrcrecordid>eNrjZDAISEzOTkxPVSguKSpNLiktSlVIzEtRSEtMKspMTizJzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhuYGpiYG5k5GxsSoAQB0OyuV</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Package structure and fabricating method thereof</title><source>esp@cenet</source><creator>Hou, Shang-Yun ; Huang, Kuan-Yu ; Huang, Sung-Hui</creator><creatorcontrib>Hou, Shang-Yun ; Huang, Kuan-Yu ; Huang, Sung-Hui</creatorcontrib><description>A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230718&DB=EPODOC&CC=US&NR=11705407B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230718&DB=EPODOC&CC=US&NR=11705407B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hou, Shang-Yun</creatorcontrib><creatorcontrib>Huang, Kuan-Yu</creatorcontrib><creatorcontrib>Huang, Sung-Hui</creatorcontrib><title>Package structure and fabricating method thereof</title><description>A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAISEzOTkxPVSguKSpNLiktSlVIzEtRSEtMKspMTizJzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhuYGpiYG5k5GxsSoAQB0OyuV</recordid><startdate>20230718</startdate><enddate>20230718</enddate><creator>Hou, Shang-Yun</creator><creator>Huang, Kuan-Yu</creator><creator>Huang, Sung-Hui</creator><scope>EVB</scope></search><sort><creationdate>20230718</creationdate><title>Package structure and fabricating method thereof</title><author>Hou, Shang-Yun ; Huang, Kuan-Yu ; Huang, Sung-Hui</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11705407B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hou, Shang-Yun</creatorcontrib><creatorcontrib>Huang, Kuan-Yu</creatorcontrib><creatorcontrib>Huang, Sung-Hui</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hou, Shang-Yun</au><au>Huang, Kuan-Yu</au><au>Huang, Sung-Hui</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Package structure and fabricating method thereof</title><date>2023-07-18</date><risdate>2023</risdate><abstract>A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Package structure and fabricating method thereof |
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