Methods and apparatus for cache-aware task scheduling in a symmetric multi-processing (SMP) environment

Methods and apparatus for cache-aware task scheduling in a symmetric multi-processing (SMP) environment

An apparatus is configured to collect information related to a first activity and analyze the collected information to determine decision data. The information is stored in a first list of the source processing core for scheduling execution of the activity by a destination processing core to avoid c...

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Bibliographische Detailangaben
Hauptverfasser: Kishore, Kamal, Vrind, Tushar, Siddappa, Raju Udava, Indukuri, Venkata Raju, Kandasamy, Balaji Somu, Kumar, Chandan
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Zusammenfassung:An apparatus is configured to collect information related to a first activity and analyze the collected information to determine decision data. The information is stored in a first list of the source processing core for scheduling execution of the activity by a destination processing core to avoid cache misses. The source processing core is configured to transmit information related to the decision data using an interrupt, to a second list associated with a scheduler of the destination processing core, if the destination processing core is currently executing a second activity having a lower priority than the first activity.