Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory con...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Meaney, Patrick J, Van Huben, Gary A, Carlough, Steven R, Zheng, Jie, Powell, Stephen J, Eickhoff, Susan M
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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