Low pin-count architecture with prioritized message arbitration and delivery

Methods and apparatus for implementing a low-pin count architecture with priority message arbitration and delivery. The architecture includes a hardware-based message arbitration unit (MAU) including a plurality of priority queues, each having a respective priority level, implemented on a first comp...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Divakaran, Sudeep, Sugumar, Suresh, Somayaji, Vishwanath
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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