PCM metal shielding for wafer testing
Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the produ...
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| creator | Allison, Matt Kothari, Jay Hamilton, Jacob Kononova, Tran Nguyen, Kim T Shapiro, Eric S |
| description | Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. The described methods entail the use of a properly patterned metal layer on the PCM dies adjacent to the product dies under test. Such patterned metal layers shield traces of the wafer probes from the circuits of the PCM dies. Various exemplary metal layer patterns are also presented. |
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Various exemplary metal layer patterns are also presented.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230606&DB=EPODOC&CC=US&NR=11670555B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230606&DB=EPODOC&CC=US&NR=11670555B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Allison, Matt</creatorcontrib><creatorcontrib>Kothari, Jay</creatorcontrib><creatorcontrib>Hamilton, Jacob</creatorcontrib><creatorcontrib>Kononova, Tran</creatorcontrib><creatorcontrib>Nguyen, Kim T</creatorcontrib><creatorcontrib>Shapiro, Eric S</creatorcontrib><title>PCM metal shielding for wafer testing</title><description>Method and devices to reduce integrated circuit fabrication process yield loss due to undesired interactions between PCMs and the wafer test probes during wafer sorting tests are disclosed. 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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING |
| title | PCM metal shielding for wafer testing |
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