Memory with adjustable TSV delay
Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatu...
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| creator | Pearson, Evan C Geidl, Anthony M Scott, Michael J Geiger, Markus H Hiscock, Dale H Gatlin, Greg S Roth, Michael Gentry, John H Matthews, Lael H |
| description | Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11670358B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11670358B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11670358B23</originalsourceid><addsrcrecordid>eNrjZFDwTc3NL6pUKM8syVBITMkqLS5JTMpJVQgJDlNISc1JrORhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGZuYGxqYWTkbGxKgBADk6JRk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Memory with adjustable TSV delay</title><source>esp@cenet</source><creator>Pearson, Evan C ; Geidl, Anthony M ; Scott, Michael J ; Geiger, Markus H ; Hiscock, Dale H ; Gatlin, Greg S ; Roth, Michael ; Gentry, John H ; Matthews, Lael H</creator><creatorcontrib>Pearson, Evan C ; Geidl, Anthony M ; Scott, Michael J ; Geiger, Markus H ; Hiscock, Dale H ; Gatlin, Greg S ; Roth, Michael ; Gentry, John H ; Matthews, Lael H</creatorcontrib><description>Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230606&DB=EPODOC&CC=US&NR=11670358B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230606&DB=EPODOC&CC=US&NR=11670358B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Pearson, Evan C</creatorcontrib><creatorcontrib>Geidl, Anthony M</creatorcontrib><creatorcontrib>Scott, Michael J</creatorcontrib><creatorcontrib>Geiger, Markus H</creatorcontrib><creatorcontrib>Hiscock, Dale H</creatorcontrib><creatorcontrib>Gatlin, Greg S</creatorcontrib><creatorcontrib>Roth, Michael</creatorcontrib><creatorcontrib>Gentry, John H</creatorcontrib><creatorcontrib>Matthews, Lael H</creatorcontrib><title>Memory with adjustable TSV delay</title><description>Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDwTc3NL6pUKM8syVBITMkqLS5JTMpJVQgJDlNISc1JrORhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGZuYGxqYWTkbGxKgBADk6JRk</recordid><startdate>20230606</startdate><enddate>20230606</enddate><creator>Pearson, Evan C</creator><creator>Geidl, Anthony M</creator><creator>Scott, Michael J</creator><creator>Geiger, Markus H</creator><creator>Hiscock, Dale H</creator><creator>Gatlin, Greg S</creator><creator>Roth, Michael</creator><creator>Gentry, John H</creator><creator>Matthews, Lael H</creator><scope>EVB</scope></search><sort><creationdate>20230606</creationdate><title>Memory with adjustable TSV delay</title><author>Pearson, Evan C ; Geidl, Anthony M ; Scott, Michael J ; Geiger, Markus H ; Hiscock, Dale H ; Gatlin, Greg S ; Roth, Michael ; Gentry, John H ; Matthews, Lael H</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11670358B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Pearson, Evan C</creatorcontrib><creatorcontrib>Geidl, Anthony M</creatorcontrib><creatorcontrib>Scott, Michael J</creatorcontrib><creatorcontrib>Geiger, Markus H</creatorcontrib><creatorcontrib>Hiscock, Dale H</creatorcontrib><creatorcontrib>Gatlin, Greg S</creatorcontrib><creatorcontrib>Roth, Michael</creatorcontrib><creatorcontrib>Gentry, John H</creatorcontrib><creatorcontrib>Matthews, Lael H</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pearson, Evan C</au><au>Geidl, Anthony M</au><au>Scott, Michael J</au><au>Geiger, Markus H</au><au>Hiscock, Dale H</au><au>Gatlin, Greg S</au><au>Roth, Michael</au><au>Gentry, John H</au><au>Matthews, Lael H</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory with adjustable TSV delay</title><date>2023-06-06</date><risdate>2023</risdate><abstract>Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | Memory with adjustable TSV delay |
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