Semiconductor package element

A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface an...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Li, Chi-Hsueh, Ho, Chung-Hsiung, Chang, Chih-Hung
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Li, Chi-Hsueh
Ho, Chung-Hsiung
Chang, Chih-Hung
description A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer, the etched surface is formed by plasma etching.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11664345B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11664345B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11664345B23</originalsourceid><addsrcrecordid>eNrjZJANTs3NTM7PSylNLskvUihITM5OTE9VSM1JzU3NK-FhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQNWpeakl8aHBhoZmZibGJqZORsbEqAEA6wokiQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package element</title><source>esp@cenet</source><creator>Li, Chi-Hsueh ; Ho, Chung-Hsiung ; Chang, Chih-Hung</creator><creatorcontrib>Li, Chi-Hsueh ; Ho, Chung-Hsiung ; Chang, Chih-Hung</creatorcontrib><description>A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer, the etched surface is formed by plasma etching.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230530&amp;DB=EPODOC&amp;CC=US&amp;NR=11664345B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20230530&amp;DB=EPODOC&amp;CC=US&amp;NR=11664345B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Li, Chi-Hsueh</creatorcontrib><creatorcontrib>Ho, Chung-Hsiung</creatorcontrib><creatorcontrib>Chang, Chih-Hung</creatorcontrib><title>Semiconductor package element</title><description>A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer, the etched surface is formed by plasma etching.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJANTs3NTM7PSylNLskvUihITM5OTE9VSM1JzU3NK-FhYE1LzClO5YXS3AyKbq4hzh66qQX58anFQNWpeakl8aHBhoZmZibGJqZORsbEqAEA6wokiQ</recordid><startdate>20230530</startdate><enddate>20230530</enddate><creator>Li, Chi-Hsueh</creator><creator>Ho, Chung-Hsiung</creator><creator>Chang, Chih-Hung</creator><scope>EVB</scope></search><sort><creationdate>20230530</creationdate><title>Semiconductor package element</title><author>Li, Chi-Hsueh ; Ho, Chung-Hsiung ; Chang, Chih-Hung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11664345B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Li, Chi-Hsueh</creatorcontrib><creatorcontrib>Ho, Chung-Hsiung</creatorcontrib><creatorcontrib>Chang, Chih-Hung</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li, Chi-Hsueh</au><au>Ho, Chung-Hsiung</au><au>Chang, Chih-Hung</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package element</title><date>2023-05-30</date><risdate>2023</risdate><abstract>A semiconductor package element includes a die, a passive layer, a conductive structure and an encapsulation layer. The die includes a first surface, a second surface and a third surface. The second surface is opposite to the first surface. The third surface is connected between the first surface and the second surface. The passive layer is disposed on the first surface and formed with a hole. The conductive structure is electrically coupled to the die through the hole. The encapsulation layer covers the first surface and the third surface of the die, wherein the passive layer is embedded in the encapsulation layer, a portion of the conductive structure is embedded in the encapsulation layer, and the other portion of the conductive structure protrudes from an etched surface of the encapsulation layer, the etched surface is formed by plasma etching.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US11664345B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor package element
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T07%3A37%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Li,%20Chi-Hsueh&rft.date=2023-05-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11664345B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true