Vertical tunneling field effect transistor with dual liner bottom spacer

Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bergendahl, Marc A, Teehan, Sean, Miller, Eric, Cheng, Kangguo, Sporre, John
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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