Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof

A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers...

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1. Verfasser:	Hsu, Chia-Ching
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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creator	Hsu, Chia-Ching
description	A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11621271B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11621271B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11621271B23</originalsourceid><addsrcrecordid>eNrjZAgKzszJTM7P082vyExJ1c3LLCkC0RBeMUROQSPY388_WFMhNzU3v6hSITk1J0chMS9FIS2_KDczLx0oXpKRn6JQkpFalJqfxsPAmpaYU5zKC6W5GRTdXEOcPXRTC_LjU4sLEpNT81JL4kODDQ3NjAyNzA2djIyJUQMAx_03fQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof</title><source>esp@cenet</source><creator>Hsu, Chia-Ching</creator><creatorcontrib>Hsu, Chia-Ching</creatorcontrib><description>A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230404&DB=EPODOC&CC=US&NR=11621271B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25562,76317</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230404&DB=EPODOC&CC=US&NR=11621271B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hsu, Chia-Ching</creatorcontrib><title>Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof</title><description>A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgKzszJTM7P082vyExJ1c3LLCkC0RBeMUROQSPY388_WFMhNzU3v6hSITk1J0chMS9FIS2_KDczLx0oXpKRn6JQkpFalJqfxsPAmpaYU5zKC6W5GRTdXEOcPXRTC_LjU4sLEpNT81JL4kODDQ3NjAyNzA2djIyJUQMAx_03fQ</recordid><startdate>20230404</startdate><enddate>20230404</enddate><creator>Hsu, Chia-Ching</creator><scope>EVB</scope></search><sort><creationdate>20230404</creationdate><title>Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof</title><author>Hsu, Chia-Ching</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11621271B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hsu, Chia-Ching</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hsu, Chia-Ching</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof</title><date>2023-04-04</date><risdate>2023</risdate><abstract>A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell includes a memory gate, a dielectric layer, two charge trapping layers and two selective gates. The memory gate is disposed on a substrate. The two charge trapping layers are at two ends of the dielectric layer, and the charge trapping layers and the dielectric layer are sandwiched by the substrate and the memory gate. The two selective gates are disposed at two opposite sides of the memory gate, thereby constituting a two bit memory cell. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.</abstract><oa>free_for_read</oa></addata></record>
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title	Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof
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