Protocol for memory power-mode control

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Richardson, Wayne S, Ware, Frederick A, Ellis, Wayne F, Kasamsetty, Kishore Ven, Lai, Lawrence, Bansal, Akash
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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