Instruction packing scheme for VLIW CPU architecture

A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction include...

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Bibliographische Detailangaben

Hauptverfasser:	Natarajan, Venkatesh, Langadi, Saya Goud, Tessarolo, Alexander
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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