Method for fabricating a semiconductor device including a gate structure with an inclined side wall

A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the f...

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Hauptverfasser: Hwang, Eui Chul, Jung, Joo Ho, Kim, Ju Youn, Lee, Sung Moon, Na, Hyung Joo, Yoo, Sang Min, Suh, Bong Seok
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creator Hwang, Eui Chul
Jung, Joo Ho
Kim, Ju Youn
Lee, Sung Moon
Na, Hyung Joo
Yoo, Sang Min
Suh, Bong Seok
description A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11538807B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11538807B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11538807B23</originalsourceid><addsrcrecordid>eNqNykEKwjAQheFsXIh6h_EAgrWIXVcUN67UdRkn03YgJiWZ6vUN6gFcPfjfNzV0Zu2DhTZEaPEehVDFd4CQ-CEUvB1J82f5KcQgntxov6BDZUgaMxgjw0u0B_QfIp4tJLG5onNzM2nRJV78dmaWx8N1f1rxEBpOAxJ71uZ2KYptWVXrXb0p_zFvlA8-iA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method for fabricating a semiconductor device including a gate structure with an inclined side wall</title><source>esp@cenet</source><creator>Hwang, Eui Chul ; Jung, Joo Ho ; Kim, Ju Youn ; Lee, Sung Moon ; Na, Hyung Joo ; Yoo, Sang Min ; Suh, Bong Seok</creator><creatorcontrib>Hwang, Eui Chul ; Jung, Joo Ho ; Kim, Ju Youn ; Lee, Sung Moon ; Na, Hyung Joo ; Yoo, Sang Min ; Suh, Bong Seok</creatorcontrib><description>A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221227&amp;DB=EPODOC&amp;CC=US&amp;NR=11538807B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221227&amp;DB=EPODOC&amp;CC=US&amp;NR=11538807B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Hwang, Eui Chul</creatorcontrib><creatorcontrib>Jung, Joo Ho</creatorcontrib><creatorcontrib>Kim, Ju Youn</creatorcontrib><creatorcontrib>Lee, Sung Moon</creatorcontrib><creatorcontrib>Na, Hyung Joo</creatorcontrib><creatorcontrib>Yoo, Sang Min</creatorcontrib><creatorcontrib>Suh, Bong Seok</creatorcontrib><title>Method for fabricating a semiconductor device including a gate structure with an inclined side wall</title><description>A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNykEKwjAQheFsXIh6h_EAgrWIXVcUN67UdRkn03YgJiWZ6vUN6gFcPfjfNzV0Zu2DhTZEaPEehVDFd4CQ-CEUvB1J82f5KcQgntxov6BDZUgaMxgjw0u0B_QfIp4tJLG5onNzM2nRJV78dmaWx8N1f1rxEBpOAxJ71uZ2KYptWVXrXb0p_zFvlA8-iA</recordid><startdate>20221227</startdate><enddate>20221227</enddate><creator>Hwang, Eui Chul</creator><creator>Jung, Joo Ho</creator><creator>Kim, Ju Youn</creator><creator>Lee, Sung Moon</creator><creator>Na, Hyung Joo</creator><creator>Yoo, Sang Min</creator><creator>Suh, Bong Seok</creator><scope>EVB</scope></search><sort><creationdate>20221227</creationdate><title>Method for fabricating a semiconductor device including a gate structure with an inclined side wall</title><author>Hwang, Eui Chul ; Jung, Joo Ho ; Kim, Ju Youn ; Lee, Sung Moon ; Na, Hyung Joo ; Yoo, Sang Min ; Suh, Bong Seok</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11538807B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Hwang, Eui Chul</creatorcontrib><creatorcontrib>Jung, Joo Ho</creatorcontrib><creatorcontrib>Kim, Ju Youn</creatorcontrib><creatorcontrib>Lee, Sung Moon</creatorcontrib><creatorcontrib>Na, Hyung Joo</creatorcontrib><creatorcontrib>Yoo, Sang Min</creatorcontrib><creatorcontrib>Suh, Bong Seok</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hwang, Eui Chul</au><au>Jung, Joo Ho</au><au>Kim, Ju Youn</au><au>Lee, Sung Moon</au><au>Na, Hyung Joo</au><au>Yoo, Sang Min</au><au>Suh, Bong Seok</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for fabricating a semiconductor device including a gate structure with an inclined side wall</title><date>2022-12-27</date><risdate>2022</risdate><abstract>A semiconductor device and a method for fabricating the same, the device including an active pattern extending in a first direction on a substrate; a field insulating film surrounding a part of the active pattern; a first gate structure extending in a second direction on the active pattern and the field insulating film, a second gate structure spaced apart from the first gate structure and extending in the second direction on the active pattern and the field insulating film; and a first device isolation film between the first and second gate structure, wherein a side wall of the first gate structure facing the first device isolation film includes an inclined surface having an acute angle with respect to an upper surface of the active pattern, and a lowermost surface of the first device isolation film is lower than or substantially coplanar with an uppermost surface of the field insulating film.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Method for fabricating a semiconductor device including a gate structure with an inclined side wall
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T07%3A11%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Hwang,%20Eui%20Chul&rft.date=2022-12-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11538807B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true