Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate
A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Tsai, Tsung-Ying Feng, Li-Wei Liu, Tzu-Tsen Ho, Chien-Ting Wang, Ying-Chiao |
| description | A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11508614B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11508614B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11508614B23</originalsourceid><addsrcrecordid>eNqNir0KwjAURrs4iPoO1wcQrH84K4qLkzqX2-RLeqFNQpLW11dBd6cD55xxYa7IjdfkDRkfO3GWEjpR3uleZR9JYxAFanj4NMUhQBNLJMshUY38BBzVfZS3ryVTKw6J2OmftJwxLUaG24TZl5Nifj7dj5cFgq-QAis45OpxK8vtcr8rN4fV-p_nBUsWP0s</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate</title><source>esp@cenet</source><creator>Tsai, Tsung-Ying ; Feng, Li-Wei ; Liu, Tzu-Tsen ; Ho, Chien-Ting ; Wang, Ying-Chiao</creator><creatorcontrib>Tsai, Tsung-Ying ; Feng, Li-Wei ; Liu, Tzu-Tsen ; Ho, Chien-Ting ; Wang, Ying-Chiao</creatorcontrib><description>A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221122&DB=EPODOC&CC=US&NR=11508614B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221122&DB=EPODOC&CC=US&NR=11508614B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tsai, Tsung-Ying</creatorcontrib><creatorcontrib>Feng, Li-Wei</creatorcontrib><creatorcontrib>Liu, Tzu-Tsen</creatorcontrib><creatorcontrib>Ho, Chien-Ting</creatorcontrib><creatorcontrib>Wang, Ying-Chiao</creatorcontrib><title>Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate</title><description>A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNir0KwjAURrs4iPoO1wcQrH84K4qLkzqX2-RLeqFNQpLW11dBd6cD55xxYa7IjdfkDRkfO3GWEjpR3uleZR9JYxAFanj4NMUhQBNLJMshUY38BBzVfZS3ryVTKw6J2OmftJwxLUaG24TZl5Nifj7dj5cFgq-QAis45OpxK8vtcr8rN4fV-p_nBUsWP0s</recordid><startdate>20221122</startdate><enddate>20221122</enddate><creator>Tsai, Tsung-Ying</creator><creator>Feng, Li-Wei</creator><creator>Liu, Tzu-Tsen</creator><creator>Ho, Chien-Ting</creator><creator>Wang, Ying-Chiao</creator><scope>EVB</scope></search><sort><creationdate>20221122</creationdate><title>Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate</title><author>Tsai, Tsung-Ying ; Feng, Li-Wei ; Liu, Tzu-Tsen ; Ho, Chien-Ting ; Wang, Ying-Chiao</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11508614B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Tsai, Tsung-Ying</creatorcontrib><creatorcontrib>Feng, Li-Wei</creatorcontrib><creatorcontrib>Liu, Tzu-Tsen</creatorcontrib><creatorcontrib>Ho, Chien-Ting</creatorcontrib><creatorcontrib>Wang, Ying-Chiao</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tsai, Tsung-Ying</au><au>Feng, Li-Wei</au><au>Liu, Tzu-Tsen</au><au>Ho, Chien-Ting</au><au>Wang, Ying-Chiao</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate</title><date>2022-11-22</date><risdate>2022</risdate><abstract>A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US11508614B2 |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T20%3A29%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tsai,%20Tsung-Ying&rft.date=2022-11-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11508614B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |