Semiconductor device and manufacturing method thereof

A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Huang, Shan-Shi, Hsu, Chih-Kai, Lee, Chiu-Te, Hsu, Chia-Jung, Fu, Ssu-I, Yang, Ching-Chung, Li, Nien-Chung, Lee, Wen-Fang, Lin, Yu-Hsiang, Chiu, Chun-Ya, Chen, Chin-Hung, Li, Shin-Hung, Hsiung, Chang-Po
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Huang, Shan-Shi
Hsu, Chih-Kai
Lee, Chiu-Te
Hsu, Chia-Jung
Fu, Ssu-I
Yang, Ching-Chung
Li, Nien-Chung
Lee, Wen-Fang
Lin, Yu-Hsiang
Chiu, Chun-Ya
Chen, Chin-Hung
Li, Shin-Hung
Hsiung, Chang-Po
description A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11495681B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11495681B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11495681B23</originalsourceid><addsrcrecordid>eNrjZDANTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE3MK01LTC4pLcrMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGJpamZhaGTkbGxKgBAKRyLdo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device and manufacturing method thereof</title><source>esp@cenet</source><creator>Huang, Shan-Shi ; Hsu, Chih-Kai ; Lee, Chiu-Te ; Hsu, Chia-Jung ; Fu, Ssu-I ; Yang, Ching-Chung ; Li, Nien-Chung ; Lee, Wen-Fang ; Lin, Yu-Hsiang ; Chiu, Chun-Ya ; Chen, Chin-Hung ; Li, Shin-Hung ; Hsiung, Chang-Po</creator><creatorcontrib>Huang, Shan-Shi ; Hsu, Chih-Kai ; Lee, Chiu-Te ; Hsu, Chia-Jung ; Fu, Ssu-I ; Yang, Ching-Chung ; Li, Nien-Chung ; Lee, Wen-Fang ; Lin, Yu-Hsiang ; Chiu, Chun-Ya ; Chen, Chin-Hung ; Li, Shin-Hung ; Hsiung, Chang-Po</creatorcontrib><description>A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221108&amp;DB=EPODOC&amp;CC=US&amp;NR=11495681B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221108&amp;DB=EPODOC&amp;CC=US&amp;NR=11495681B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Huang, Shan-Shi</creatorcontrib><creatorcontrib>Hsu, Chih-Kai</creatorcontrib><creatorcontrib>Lee, Chiu-Te</creatorcontrib><creatorcontrib>Hsu, Chia-Jung</creatorcontrib><creatorcontrib>Fu, Ssu-I</creatorcontrib><creatorcontrib>Yang, Ching-Chung</creatorcontrib><creatorcontrib>Li, Nien-Chung</creatorcontrib><creatorcontrib>Lee, Wen-Fang</creatorcontrib><creatorcontrib>Lin, Yu-Hsiang</creatorcontrib><creatorcontrib>Chiu, Chun-Ya</creatorcontrib><creatorcontrib>Chen, Chin-Hung</creatorcontrib><creatorcontrib>Li, Shin-Hung</creatorcontrib><creatorcontrib>Hsiung, Chang-Po</creatorcontrib><title>Semiconductor device and manufacturing method thereof</title><description>A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDANTs3NTM7PSylNLskvUkhJLctMTlVIzEtRyE3MK01LTC4pLcrMS1fITS3JyE9RKMlILUrNT-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGJpamZhaGTkbGxKgBAKRyLdo</recordid><startdate>20221108</startdate><enddate>20221108</enddate><creator>Huang, Shan-Shi</creator><creator>Hsu, Chih-Kai</creator><creator>Lee, Chiu-Te</creator><creator>Hsu, Chia-Jung</creator><creator>Fu, Ssu-I</creator><creator>Yang, Ching-Chung</creator><creator>Li, Nien-Chung</creator><creator>Lee, Wen-Fang</creator><creator>Lin, Yu-Hsiang</creator><creator>Chiu, Chun-Ya</creator><creator>Chen, Chin-Hung</creator><creator>Li, Shin-Hung</creator><creator>Hsiung, Chang-Po</creator><scope>EVB</scope></search><sort><creationdate>20221108</creationdate><title>Semiconductor device and manufacturing method thereof</title><author>Huang, Shan-Shi ; Hsu, Chih-Kai ; Lee, Chiu-Te ; Hsu, Chia-Jung ; Fu, Ssu-I ; Yang, Ching-Chung ; Li, Nien-Chung ; Lee, Wen-Fang ; Lin, Yu-Hsiang ; Chiu, Chun-Ya ; Chen, Chin-Hung ; Li, Shin-Hung ; Hsiung, Chang-Po</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11495681B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Huang, Shan-Shi</creatorcontrib><creatorcontrib>Hsu, Chih-Kai</creatorcontrib><creatorcontrib>Lee, Chiu-Te</creatorcontrib><creatorcontrib>Hsu, Chia-Jung</creatorcontrib><creatorcontrib>Fu, Ssu-I</creatorcontrib><creatorcontrib>Yang, Ching-Chung</creatorcontrib><creatorcontrib>Li, Nien-Chung</creatorcontrib><creatorcontrib>Lee, Wen-Fang</creatorcontrib><creatorcontrib>Lin, Yu-Hsiang</creatorcontrib><creatorcontrib>Chiu, Chun-Ya</creatorcontrib><creatorcontrib>Chen, Chin-Hung</creatorcontrib><creatorcontrib>Li, Shin-Hung</creatorcontrib><creatorcontrib>Hsiung, Chang-Po</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Huang, Shan-Shi</au><au>Hsu, Chih-Kai</au><au>Lee, Chiu-Te</au><au>Hsu, Chia-Jung</au><au>Fu, Ssu-I</au><au>Yang, Ching-Chung</au><au>Li, Nien-Chung</au><au>Lee, Wen-Fang</au><au>Lin, Yu-Hsiang</au><au>Chiu, Chun-Ya</au><au>Chen, Chin-Hung</au><au>Li, Shin-Hung</au><au>Hsiung, Chang-Po</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device and manufacturing method thereof</title><date>2022-11-08</date><risdate>2022</risdate><abstract>A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US11495681B2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor device and manufacturing method thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-28T18%3A57%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Huang,%20Shan-Shi&rft.date=2022-11-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11495681B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true