Array of vertical transistors and method used in forming an array of vertical transistors

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in indi...

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Hauptverfasser: McDaniel, Terrence B, Yang, Sheng-Wei, Lee, Yi Fang, Heineck, Lars P, Guha, Jaydip, Karda, Kamal M, Sills, Scott E, Lee, Si-Woo, Torek, Kevin J
Format: Patent
Sprache:eng
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