Speculative cache storage region

An apparatus (2) comprises processing circuitry (4) to perform speculative execution of instructions; a main cache storage region (30); a speculative cache storage region (32); and cache control circuitry (34) to allocate an entry, for which allocation is caused by a speculative memory access trigge...

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Bibliographische Detailangaben
1. Verfasser: Grisenthwaite, Richard Roy
Format: Patent
Sprache:eng
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