Semiconductor memory device
A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direc...
Gespeichert in:
Hauptverfasser: | , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Ishihara, Hanae Shirai, Kaito |
description | A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11444022B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11444022B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11444022B23</originalsourceid><addsrcrecordid>eNrjZJAOTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhiYmJgZGRk5GxsSoAQCXfyPC</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor memory device</title><source>esp@cenet</source><creator>Ishihara, Hanae ; Shirai, Kaito</creator><creatorcontrib>Ishihara, Hanae ; Shirai, Kaito</creatorcontrib><description>A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220913&DB=EPODOC&CC=US&NR=11444022B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76418</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220913&DB=EPODOC&CC=US&NR=11444022B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ishihara, Hanae</creatorcontrib><creatorcontrib>Shirai, Kaito</creatorcontrib><title>Semiconductor memory device</title><description>A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOTs3NTM7PSylNLskvUshNzc0vqlRISS3LTE7lYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxQWJyal5qSXxocGGhiYmJgZGRk5GxsSoAQCXfyPC</recordid><startdate>20220913</startdate><enddate>20220913</enddate><creator>Ishihara, Hanae</creator><creator>Shirai, Kaito</creator><scope>EVB</scope></search><sort><creationdate>20220913</creationdate><title>Semiconductor memory device</title><author>Ishihara, Hanae ; Shirai, Kaito</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11444022B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ishihara, Hanae</creatorcontrib><creatorcontrib>Shirai, Kaito</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ishihara, Hanae</au><au>Shirai, Kaito</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor memory device</title><date>2022-09-13</date><risdate>2022</risdate><abstract>A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US11444022B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor memory device |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T10%3A46%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ishihara,%20Hanae&rft.date=2022-09-13&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11444022B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |