Semiconductor devices with circuit and external dummy areas

A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy g...

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Hauptverfasser: Nam, Seonah, Park, Sungho, Kang, Byungju, Kim, Hyelim, Kim, Byungsung, Qian, Yubo
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creator Nam, Seonah
Park, Sungho
Kang, Byungju
Kim, Hyelim
Kim, Byungsung
Qian, Yubo
description A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11410994B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11410994B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11410994B23</originalsourceid><addsrcrecordid>eNrjZLAOTs3NTM7PSylNLskvUkhJLctMTi1WKM8syVBIzixKLs0sUUjMS1FIrShJLcpLzFFIKc3NrVRILEpNLOZhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGJoYGlpYmTkbGxKgBAOMuL-8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor devices with circuit and external dummy areas</title><source>esp@cenet</source><creator>Nam, Seonah ; Park, Sungho ; Kang, Byungju ; Kim, Hyelim ; Kim, Byungsung ; Qian, Yubo</creator><creatorcontrib>Nam, Seonah ; Park, Sungho ; Kang, Byungju ; Kim, Hyelim ; Kim, Byungsung ; Qian, Yubo</creatorcontrib><description>A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220809&amp;DB=EPODOC&amp;CC=US&amp;NR=11410994B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220809&amp;DB=EPODOC&amp;CC=US&amp;NR=11410994B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Nam, Seonah</creatorcontrib><creatorcontrib>Park, Sungho</creatorcontrib><creatorcontrib>Kang, Byungju</creatorcontrib><creatorcontrib>Kim, Hyelim</creatorcontrib><creatorcontrib>Kim, Byungsung</creatorcontrib><creatorcontrib>Qian, Yubo</creatorcontrib><title>Semiconductor devices with circuit and external dummy areas</title><description>A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAOTs3NTM7PSylNLskvUkhJLctMTi1WKM8syVBIzixKLs0sUUjMS1FIrShJLcpLzFFIKc3NrVRILEpNLOZhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGJoYGlpYmTkbGxKgBAOMuL-8</recordid><startdate>20220809</startdate><enddate>20220809</enddate><creator>Nam, Seonah</creator><creator>Park, Sungho</creator><creator>Kang, Byungju</creator><creator>Kim, Hyelim</creator><creator>Kim, Byungsung</creator><creator>Qian, Yubo</creator><scope>EVB</scope></search><sort><creationdate>20220809</creationdate><title>Semiconductor devices with circuit and external dummy areas</title><author>Nam, Seonah ; Park, Sungho ; Kang, Byungju ; Kim, Hyelim ; Kim, Byungsung ; Qian, Yubo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11410994B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Nam, Seonah</creatorcontrib><creatorcontrib>Park, Sungho</creatorcontrib><creatorcontrib>Kang, Byungju</creatorcontrib><creatorcontrib>Kim, Hyelim</creatorcontrib><creatorcontrib>Kim, Byungsung</creatorcontrib><creatorcontrib>Qian, Yubo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nam, Seonah</au><au>Park, Sungho</au><au>Kang, Byungju</au><au>Kim, Hyelim</au><au>Kim, Byungsung</au><au>Qian, Yubo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor devices with circuit and external dummy areas</title><date>2022-08-09</date><risdate>2022</risdate><abstract>A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor devices with circuit and external dummy areas
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T19%3A04%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Nam,%20Seonah&rft.date=2022-08-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11410994B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true