Signaling of time for communication between integrated circuits using multi-drop bus

Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integra...

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Hauptverfasser: Sauer, Matthias, O'Shea, Helena Deirdre, Rivera Espinoza, Jorge L
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creator Sauer, Matthias
O'Shea, Helena Deirdre
Rivera Espinoza, Jorge L
description Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11398926B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11398926B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11398926B23</originalsourceid><addsrcrecordid>eNqNy7EKwjAQgOEsDqK-w_kAHdqC2LWiuLfOJU0v4SC5hOSCry-CD-D0L9-_V_NEjrUndhAtCAUEGzOYGEJlMlooMqwob0QGYkGXteAGhrKpJAVq-b6heqFmyzHBWstR7az2BU-_HtT5cZ9vzwZTXLAkbZBRltfUtv1wHbrL2PX_mA_b_TmO</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Signaling of time for communication between integrated circuits using multi-drop bus</title><source>esp@cenet</source><creator>Sauer, Matthias ; O'Shea, Helena Deirdre ; Rivera Espinoza, Jorge L</creator><creatorcontrib>Sauer, Matthias ; O'Shea, Helena Deirdre ; Rivera Espinoza, Jorge L</creatorcontrib><description>Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.</description><language>eng</language><subject>ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220726&amp;DB=EPODOC&amp;CC=US&amp;NR=11398926B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220726&amp;DB=EPODOC&amp;CC=US&amp;NR=11398926B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Sauer, Matthias</creatorcontrib><creatorcontrib>O'Shea, Helena Deirdre</creatorcontrib><creatorcontrib>Rivera Espinoza, Jorge L</creatorcontrib><title>Signaling of time for communication between integrated circuits using multi-drop bus</title><description>Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.</description><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNy7EKwjAQgOEsDqK-w_kAHdqC2LWiuLfOJU0v4SC5hOSCry-CD-D0L9-_V_NEjrUndhAtCAUEGzOYGEJlMlooMqwob0QGYkGXteAGhrKpJAVq-b6heqFmyzHBWstR7az2BU-_HtT5cZ9vzwZTXLAkbZBRltfUtv1wHbrL2PX_mA_b_TmO</recordid><startdate>20220726</startdate><enddate>20220726</enddate><creator>Sauer, Matthias</creator><creator>O'Shea, Helena Deirdre</creator><creator>Rivera Espinoza, Jorge L</creator><scope>EVB</scope></search><sort><creationdate>20220726</creationdate><title>Signaling of time for communication between integrated circuits using multi-drop bus</title><author>Sauer, Matthias ; O'Shea, Helena Deirdre ; Rivera Espinoza, Jorge L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11398926B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Sauer, Matthias</creatorcontrib><creatorcontrib>O'Shea, Helena Deirdre</creatorcontrib><creatorcontrib>Rivera Espinoza, Jorge L</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sauer, Matthias</au><au>O'Shea, Helena Deirdre</au><au>Rivera Espinoza, Jorge L</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Signaling of time for communication between integrated circuits using multi-drop bus</title><date>2022-07-26</date><risdate>2022</risdate><abstract>Embodiments relate to including information in a data packet transmitted by a transmitting integrated circuit (e.g., SOC) to account for a time delay associated with an unsuccessful arbitration attempt to send the data packet over a multi-drop bus. The unsuccessful arbitration attempt by the integrated circuit may delay the transmission of the data packet until the multi-drop bus becomes available for the integrated circuit to send the data packet. The data packet includes a data field to include time delay information caused by the unsuccessful arbitration attempt. A receiving integrated circuit may determine the time that the data packet would have been sent out from the transmitting integrated circuit absent the unsuccessful arbitration attempt based on the delay information. Embodiments also relate to a synchronization generator circuit in an integrated circuit that generates timing signals indicating times at which periodic events occur at another integrated circuit.</abstract><oa>free_for_read</oa></addata></record>
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subjects ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Signaling of time for communication between integrated circuits using multi-drop bus
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T10%3A24%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Sauer,%20Matthias&rft.date=2022-07-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11398926B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true