Charge trap memory devices
The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self...
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| creator | Robson, Norman W Katz, Robert Kirihata, Toshiaki Khan, Faraz Anand, Darren L Moy, Dan |
| description | The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor. |
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The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220621&DB=EPODOC&CC=US&NR=11367734B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220621&DB=EPODOC&CC=US&NR=11367734B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Robson, Norman W</creatorcontrib><creatorcontrib>Katz, Robert</creatorcontrib><creatorcontrib>Kirihata, Toshiaki</creatorcontrib><creatorcontrib>Khan, Faraz</creatorcontrib><creatorcontrib>Anand, Darren L</creatorcontrib><creatorcontrib>Moy, Dan</creatorcontrib><title>Charge trap memory devices</title><description>The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. 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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
| title | Charge trap memory devices |
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