Low-power multi-stage/multi-segment content addressable memory device
Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first...
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| creator | Deshpande, Chetan Garg, Ritesh Chen, Yi-Wei Jedhe, Gajanan Sahebrao Narvekar, Gaurang Prabhakar |
| description | Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage. |
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Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220524&DB=EPODOC&CC=US&NR=11342022B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220524&DB=EPODOC&CC=US&NR=11342022B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Deshpande, Chetan</creatorcontrib><creatorcontrib>Garg, Ritesh</creatorcontrib><creatorcontrib>Chen, Yi-Wei</creatorcontrib><creatorcontrib>Jedhe, Gajanan Sahebrao</creatorcontrib><creatorcontrib>Narvekar, Gaurang Prabhakar</creatorcontrib><title>Low-power multi-stage/multi-segment content addressable memory device</title><description>Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHD1yS_XLcgvTy1SyC3NKcnULS5JTE_Vh7JT03NT80oUkvPzSkB0YkpKUWpxcWJSTqpCbmpuflGlQkpqWWZyKg8Da1piTnEqL5TmZlB0cw1x9tBNLciPTy0uSExOzUstiQ8NNjQ0NjEyMDJyMjImRg0AN_Yzzg</recordid><startdate>20220524</startdate><enddate>20220524</enddate><creator>Deshpande, Chetan</creator><creator>Garg, Ritesh</creator><creator>Chen, Yi-Wei</creator><creator>Jedhe, Gajanan Sahebrao</creator><creator>Narvekar, Gaurang Prabhakar</creator><scope>EVB</scope></search><sort><creationdate>20220524</creationdate><title>Low-power multi-stage/multi-segment content addressable memory device</title><author>Deshpande, Chetan ; Garg, Ritesh ; Chen, Yi-Wei ; Jedhe, Gajanan Sahebrao ; Narvekar, Gaurang Prabhakar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11342022B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Deshpande, Chetan</creatorcontrib><creatorcontrib>Garg, Ritesh</creatorcontrib><creatorcontrib>Chen, Yi-Wei</creatorcontrib><creatorcontrib>Jedhe, Gajanan Sahebrao</creatorcontrib><creatorcontrib>Narvekar, Gaurang Prabhakar</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Deshpande, Chetan</au><au>Garg, Ritesh</au><au>Chen, Yi-Wei</au><au>Jedhe, Gajanan Sahebrao</au><au>Narvekar, Gaurang Prabhakar</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Low-power multi-stage/multi-segment content addressable memory device</title><date>2022-05-24</date><risdate>2022</risdate><abstract>Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Low-power multi-stage/multi-segment content addressable memory device |
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