Clock gating cell with low power and integrated circuit including the same

An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-inpu...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Lee, Dalhee, Kang, Byounggon
Format: Patent
Sprache:eng
Schlagworte:
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