Memory test circuit

A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yao, Tse-Hua, Lin, Yu-Tao, Chen, Yi-Fan
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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