Reducing the memory load time for logic simulator by leveraging architecture simulator

A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the mem...

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Hauptverfasser:	Britto, Vivek, Pindicura, Tharunachalam, Xia, Yan, Srivatsan, Shricharan, Dhandapani, Aishwarya
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS INFORMATION STORAGE MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING STATIC STORES
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creator	Britto, Vivek Pindicura, Tharunachalam Xia, Yan Srivatsan, Shricharan Dhandapani, Aishwarya
description	A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.
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In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. 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In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.</abstract><oa>free_for_read</oa></addata></record>
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subjects	CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS INFORMATION STORAGE MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING STATIC STORES
title	Reducing the memory load time for logic simulator by leveraging architecture simulator
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