Memory device and multi physical cells error correction method thereof

A memory device and a multiple cells error correction in a memory cell is provided. The memory device includes a plurality of memory cells and a memory control circuit. Each of the memory cells includes a first type physical cell and a second type physical cell. The memory control circuit is coupled...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Cheung, Ngatik, Shieh, Ming-Huei, Lin, Chi-Shun, Lien, Chuen-Der, Lim, Seow Fong
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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