Completion logic performing early commitment of a store-conditional access based on a flag

A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper l...

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Bibliographische Detailangaben

Hauptverfasser:	Williams, Derek E, Shen, Hugh, Starke, William J, Guthrie, Guy L
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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