Vector instructions for selecting and extending an unsigned sum of products of words and doublewords for accumulation

Disclosed embodiments relate to executing a vector unsigned multiplication and accumulation instruction. In one example, a processor includes fetch circuitry to fetch a vector unsigned multiplication and accumulation instruction having fields for an opcode, first and second source identifiers, a des...

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Bibliographische Detailangaben

Hauptverfasser:	Ould-Ahmed-Vall, Elmoustapha, Murray, Carl, Charney, Mark J, Madduri, Venkateswara R, Valentine, Robert, Corbal, Jesus
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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