Memory with adaptive slow-cell data compression
An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the...
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| creator | Berman, Amit |
| description | An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells. |
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determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220125&DB=EPODOC&CC=US&NR=11232844B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220125&DB=EPODOC&CC=US&NR=11232844B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Berman, Amit</creatorcontrib><title>Memory with adaptive slow-cell data compression</title><description>An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3Tc3NL6pUKM8syVBITEksKMksS1Uozskv101OzclRSEksSVRIzs8tKEotLs7Mz-NhYE1LzClO5YXS3AyKbq4hzh66qQX58anFBYnJqXmpJfGhwYaGRsZGFiYmTkbGxKgBAEHTKz0</recordid><startdate>20220125</startdate><enddate>20220125</enddate><creator>Berman, Amit</creator><scope>EVB</scope></search><sort><creationdate>20220125</creationdate><title>Memory with adaptive slow-cell data compression</title><author>Berman, Amit</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11232844B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Berman, Amit</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Berman, Amit</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Memory with adaptive slow-cell data compression</title><date>2022-01-25</date><risdate>2022</risdate><abstract>An apparatus and method are provided for memory programming, including receiving a first write data unit including a plurality of data bits; programming by at least one pulse the plurality of data bits to the plurality of memory cells; determining if a number of cells successfully programmed by the at least one pulse is less than a threshold; and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a sparse vector of unsuccessfully programmed data bits, receiving another write data unit, concatenating the vector based on the other write data unit, and programming the concatenated vector to another plurality of memory cells.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES |
| title | Memory with adaptive slow-cell data compression |
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