Clock delay circuit

A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first in...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hashempour, Hamidreza, Keekstra, Ids Christiaan, Verlinden, Jos
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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