Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices

Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices

The first type of semiconductor device includes a first fin structure extending in a first direction, a first gate, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first s...

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Hauptverfasser: Lin, Jiefeng Jeff, Liaw, Jhon Jhy, Yu, Dian-Sheg, Lin, Chih-Yung, Yang, Hsiao-Lan
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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creator Lin, Jiefeng Jeff
Liaw, Jhon Jhy
Yu, Dian-Sheg
Lin, Chih-Yung
Yang, Hsiao-Lan
description The first type of semiconductor device includes a first fin structure extending in a first direction, a first gate, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first slot contact has a first slot contact dimension measured in the first direction. A second type of semiconductor device includes: a second fin structure extending in a third direction, a second gate, and a second slot contact disposed over the second fin structure. The second gate extends in a fourth direction and has a second gate dimension measured in the third direction. The second slot contact has a second slot contact dimension measured in the third direction. The second slot contact dimension is greater than the second gate dimension and greater than the first slot contact dimension.
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subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
title Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices
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