Static and intermittent dynamic multi-bias core for dual pad voltage level shifter

Static and intermittent dynamic multi-bias core for dual pad voltage level shifter

An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first bi...

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Hauptverfasser: Presswala, Aliasgar, Tan, Chiew-Guan, Chen, Wilson Jianbo, Jalilizeinali, Reza
Format: Patent
Sprache:eng
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BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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creator Presswala, Aliasgar
Tan, Chiew-Guan
Chen, Wilson Jianbo
Jalilizeinali, Reza
description An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11171649B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11171649B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11171649B13</originalsourceid><addsrcrecordid>eNqNjDsOwjAMQLMwIOAO5gAdIhCIFQRipjBXJnHBkvNR4lbi9nTgAExveE9vbm6torIDjB44KpXAqhQV_CdimEQYRLl5MlZwqRD0qYAfUCCjhzGJ4otAaCSB-uZ-OizNrEeptPpxYdaX8_10bSinjmpGR5G0e7TW2r3dbQ9Hu_mn-QIb7Dgv</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Static and intermittent dynamic multi-bias core for dual pad voltage level shifter</title><source>esp@cenet</source><creator>Presswala, Aliasgar ; Tan, Chiew-Guan ; Chen, Wilson Jianbo ; Jalilizeinali, Reza</creator><creatorcontrib>Presswala, Aliasgar ; Tan, Chiew-Guan ; Chen, Wilson Jianbo ; Jalilizeinali, Reza</creatorcontrib><description>An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211109&amp;DB=EPODOC&amp;CC=US&amp;NR=11171649B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211109&amp;DB=EPODOC&amp;CC=US&amp;NR=11171649B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Presswala, Aliasgar</creatorcontrib><creatorcontrib>Tan, Chiew-Guan</creatorcontrib><creatorcontrib>Chen, Wilson Jianbo</creatorcontrib><creatorcontrib>Jalilizeinali, Reza</creatorcontrib><title>Static and intermittent dynamic multi-bias core for dual pad voltage level shifter</title><description>An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjDsOwjAMQLMwIOAO5gAdIhCIFQRipjBXJnHBkvNR4lbi9nTgAExveE9vbm6torIDjB44KpXAqhQV_CdimEQYRLl5MlZwqRD0qYAfUCCjhzGJ4otAaCSB-uZ-OizNrEeptPpxYdaX8_10bSinjmpGR5G0e7TW2r3dbQ9Hu_mn-QIb7Dgv</recordid><startdate>20211109</startdate><enddate>20211109</enddate><creator>Presswala, Aliasgar</creator><creator>Tan, Chiew-Guan</creator><creator>Chen, Wilson Jianbo</creator><creator>Jalilizeinali, Reza</creator><scope>EVB</scope></search><sort><creationdate>20211109</creationdate><title>Static and intermittent dynamic multi-bias core for dual pad voltage level shifter</title><author>Presswala, Aliasgar ; Tan, Chiew-Guan ; Chen, Wilson Jianbo ; Jalilizeinali, Reza</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11171649B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>Presswala, Aliasgar</creatorcontrib><creatorcontrib>Tan, Chiew-Guan</creatorcontrib><creatorcontrib>Chen, Wilson Jianbo</creatorcontrib><creatorcontrib>Jalilizeinali, Reza</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Presswala, Aliasgar</au><au>Tan, Chiew-Guan</au><au>Chen, Wilson Jianbo</au><au>Jalilizeinali, Reza</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Static and intermittent dynamic multi-bias core for dual pad voltage level shifter</title><date>2021-11-09</date><risdate>2021</risdate><abstract>An output driver in an integrated circuit includes a voltage shifter. The output driver has a low voltage section configured to provide a low voltage signal responsive to an input signal and a high voltage section configured to provide a high voltage signal responsive to the input signal. A first biasing circuit is configured to provide a bias to a first transistor in the high voltage section such that the bias is modified during a transition in the output signal. A second biasing circuit is configured to turn on a second transistor in the high voltage section when the output signal is at a low voltage level. The second transistor is configured to discharge a terminal of the first transistor. The input signal switches between 0 Volts and 0.9 Volts. The output signal switches between 0 Volts and 1.2 Volts or between 0 Volts and 1.8 Volts.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title Static and intermittent dynamic multi-bias core for dual pad voltage level shifter
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T12%3A30%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Presswala,%20Aliasgar&rft.date=2021-11-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11171649B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true