Chip interconnection structure, wafer interconnection structure and method for manufacturing the same

Chip interconnection structure, wafer interconnection structure and method for manufacturing the same

A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The...

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Hauptverfasser: Yi, Hongsheng, Wang, Jiaqi, Ye, Guoliang
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Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Yi, Hongsheng
Wang, Jiaqi
Ye, Guoliang
description A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Chip interconnection structure, wafer interconnection structure and method for manufacturing the same
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