Multi-core systolic processor system for neural network processing
At least a subset of first processing units of a first arrangement of a first systolic processing chip is assigned to a first layer of a neural network and at least a subset of second processing units of a second arrangement of the first systolic processing chip is assigned to a second layer of the...
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| creator | Franca-Neto, Luiz M |
| description | At least a subset of first processing units of a first arrangement of a first systolic processing chip is assigned to a first layer of a neural network and at least a subset of second processing units of a second arrangement of the first systolic processing chip is assigned to a second layer of the neural network. At least a subset of third processing units of a third arrangement of a second systolic processing chip is assigned to a third layer of the neural network. Input data is processed using the subset of the first processing units to generate first activation output values. The first activation output values are systollically pulsed to the subset of the second processing units and processed to generate second activation output values. The second activation output values are processed using the subset of the third processing units of the second systolic processing chip. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11164074B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11164074B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11164074B23</originalsourceid><addsrcrecordid>eNrjZHDyLc0pydRNzi9KVSiuLC7Jz8lMVigoyk9OLS7OLwILpeYqpAGZeamlRYk5QKqkPL8oG6YmMy-dh4E1LTGnOJUXSnMzKLq5hjh76KYW5MenFhckJqcCNcWHBhsaGpqZGJibOBkZE6MGALLXMyI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Multi-core systolic processor system for neural network processing</title><source>esp@cenet</source><creator>Franca-Neto, Luiz M</creator><creatorcontrib>Franca-Neto, Luiz M</creatorcontrib><description>At least a subset of first processing units of a first arrangement of a first systolic processing chip is assigned to a first layer of a neural network and at least a subset of second processing units of a second arrangement of the first systolic processing chip is assigned to a second layer of the neural network. At least a subset of third processing units of a third arrangement of a second systolic processing chip is assigned to a third layer of the neural network. Input data is processed using the subset of the first processing units to generate first activation output values. The first activation output values are systollically pulsed to the subset of the second processing units and processed to generate second activation output values. The second activation output values are processed using the subset of the third processing units of the second systolic processing chip.</description><language>eng</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211102&DB=EPODOC&CC=US&NR=11164074B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211102&DB=EPODOC&CC=US&NR=11164074B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Franca-Neto, Luiz M</creatorcontrib><title>Multi-core systolic processor system for neural network processing</title><description>At least a subset of first processing units of a first arrangement of a first systolic processing chip is assigned to a first layer of a neural network and at least a subset of second processing units of a second arrangement of the first systolic processing chip is assigned to a second layer of the neural network. At least a subset of third processing units of a third arrangement of a second systolic processing chip is assigned to a third layer of the neural network. Input data is processed using the subset of the first processing units to generate first activation output values. The first activation output values are systollically pulsed to the subset of the second processing units and processed to generate second activation output values. The second activation output values are processed using the subset of the third processing units of the second systolic processing chip.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDyLc0pydRNzi9KVSiuLC7Jz8lMVigoyk9OLS7OLwILpeYqpAGZeamlRYk5QKqkPL8oG6YmMy-dh4E1LTGnOJUXSnMzKLq5hjh76KYW5MenFhckJqcCNcWHBhsaGpqZGJibOBkZE6MGALLXMyI</recordid><startdate>20211102</startdate><enddate>20211102</enddate><creator>Franca-Neto, Luiz M</creator><scope>EVB</scope></search><sort><creationdate>20211102</creationdate><title>Multi-core systolic processor system for neural network processing</title><author>Franca-Neto, Luiz M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11164074B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Franca-Neto, Luiz M</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Franca-Neto, Luiz M</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Multi-core systolic processor system for neural network processing</title><date>2021-11-02</date><risdate>2021</risdate><abstract>At least a subset of first processing units of a first arrangement of a first systolic processing chip is assigned to a first layer of a neural network and at least a subset of second processing units of a second arrangement of the first systolic processing chip is assigned to a second layer of the neural network. At least a subset of third processing units of a third arrangement of a second systolic processing chip is assigned to a third layer of the neural network. Input data is processed using the subset of the first processing units to generate first activation output values. The first activation output values are systollically pulsed to the subset of the second processing units and processed to generate second activation output values. The second activation output values are processed using the subset of the third processing units of the second systolic processing chip.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Multi-core systolic processor system for neural network processing |
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