Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems
Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in...
Gespeichert in:
Hauptverfasser: | , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Ong, Biow Hiem Chen, Chii Wean Calvin Emor, Christian George Lo, Wing Yu Quek, Chieh Hsien Daycock, David A |
description | Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11158577B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11158577B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11158577B23</originalsourceid><addsrcrecordid>eNqNjLEKwkAQBdNYiPoPa69FlBBrRbGxUuuw7m2SheQu3K4RwY_XgFhbveExzDh5ndjq4BTKEKHEWxRCE19BKxQDN0wWgxcCx70QKzzEaqDgDckULAzs7mTSM6ihREIdiDtdAHoHkRs0dr_A8OnzI7Q6TUYlNsqz706S-WF_2R2X3IWCtUNiz1Zcz2maZpssz7er9T_OG35_SMU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems</title><source>esp@cenet</source><creator>Ong, Biow Hiem ; Chen, Chii Wean Calvin ; Emor, Christian George ; Lo, Wing Yu ; Quek, Chieh Hsien ; Daycock, David A</creator><creatorcontrib>Ong, Biow Hiem ; Chen, Chii Wean Calvin ; Emor, Christian George ; Lo, Wing Yu ; Quek, Chieh Hsien ; Daycock, David A</creatorcontrib><description>Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211026&DB=EPODOC&CC=US&NR=11158577B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20211026&DB=EPODOC&CC=US&NR=11158577B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ong, Biow Hiem</creatorcontrib><creatorcontrib>Chen, Chii Wean Calvin</creatorcontrib><creatorcontrib>Emor, Christian George</creatorcontrib><creatorcontrib>Lo, Wing Yu</creatorcontrib><creatorcontrib>Quek, Chieh Hsien</creatorcontrib><creatorcontrib>Daycock, David A</creatorcontrib><title>Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems</title><description>Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjLEKwkAQBdNYiPoPa69FlBBrRbGxUuuw7m2SheQu3K4RwY_XgFhbveExzDh5ndjq4BTKEKHEWxRCE19BKxQDN0wWgxcCx70QKzzEaqDgDckULAzs7mTSM6ihREIdiDtdAHoHkRs0dr_A8OnzI7Q6TUYlNsqz706S-WF_2R2X3IWCtUNiz1Zcz2maZpssz7er9T_OG35_SMU</recordid><startdate>20211026</startdate><enddate>20211026</enddate><creator>Ong, Biow Hiem</creator><creator>Chen, Chii Wean Calvin</creator><creator>Emor, Christian George</creator><creator>Lo, Wing Yu</creator><creator>Quek, Chieh Hsien</creator><creator>Daycock, David A</creator><scope>EVB</scope></search><sort><creationdate>20211026</creationdate><title>Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems</title><author>Ong, Biow Hiem ; Chen, Chii Wean Calvin ; Emor, Christian George ; Lo, Wing Yu ; Quek, Chieh Hsien ; Daycock, David A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11158577B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ong, Biow Hiem</creatorcontrib><creatorcontrib>Chen, Chii Wean Calvin</creatorcontrib><creatorcontrib>Emor, Christian George</creatorcontrib><creatorcontrib>Lo, Wing Yu</creatorcontrib><creatorcontrib>Quek, Chieh Hsien</creatorcontrib><creatorcontrib>Daycock, David A</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ong, Biow Hiem</au><au>Chen, Chii Wean Calvin</au><au>Emor, Christian George</au><au>Lo, Wing Yu</au><au>Quek, Chieh Hsien</au><au>Daycock, David A</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems</title><date>2021-10-26</date><risdate>2021</risdate><abstract>Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US11158577B2 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Methods for fabricating microelectronic devices with contacts to conductive staircase steps, and related devices and systems |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T11%3A19%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ong,%20Biow%20Hiem&rft.date=2021-10-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11158577B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |