Semiconductor device with a passivation layer and method for producing thereof

Semiconductor device with a passivation layer and method for producing thereof

A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation l...

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Hauptverfasser: Kabakow, Andre, Rupp, Roland, Konrath, Jens Peter, Hecht, Christian
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Kabakow, Andre
Rupp, Roland
Konrath, Jens Peter
Hecht, Christian
description A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11158557B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11158557B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11158557B23</originalsourceid><addsrcrecordid>eNqNyzEOwjAMQNEuDAi4gzkAQ0ARzCAQE0thrqzEIZbaOEpMEbenAwdg-sv78-bW0sBOkn85lQKeRnYEb9YICBlr5RGVJUGPHyqAycNAGsVDmHguMo2cnqCRCklYNrOAfaXVr4tmfTnfT9cNZemoZnSUSLtHa4yxB2v3x-3uH_MFTNQ3GA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor device with a passivation layer and method for producing thereof</title><source>esp@cenet</source><creator>Kabakow, Andre ; Rupp, Roland ; Konrath, Jens Peter ; Hecht, Christian</creator><creatorcontrib>Kabakow, Andre ; Rupp, Roland ; Konrath, Jens Peter ; Hecht, Christian</creatorcontrib><description>A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211026&amp;DB=EPODOC&amp;CC=US&amp;NR=11158557B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20211026&amp;DB=EPODOC&amp;CC=US&amp;NR=11158557B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kabakow, Andre</creatorcontrib><creatorcontrib>Rupp, Roland</creatorcontrib><creatorcontrib>Konrath, Jens Peter</creatorcontrib><creatorcontrib>Hecht, Christian</creatorcontrib><title>Semiconductor device with a passivation layer and method for producing thereof</title><description>A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyzEOwjAMQNEuDAi4gzkAQ0ARzCAQE0thrqzEIZbaOEpMEbenAwdg-sv78-bW0sBOkn85lQKeRnYEb9YICBlr5RGVJUGPHyqAycNAGsVDmHguMo2cnqCRCklYNrOAfaXVr4tmfTnfT9cNZemoZnSUSLtHa4yxB2v3x-3uH_MFTNQ3GA</recordid><startdate>20211026</startdate><enddate>20211026</enddate><creator>Kabakow, Andre</creator><creator>Rupp, Roland</creator><creator>Konrath, Jens Peter</creator><creator>Hecht, Christian</creator><scope>EVB</scope></search><sort><creationdate>20211026</creationdate><title>Semiconductor device with a passivation layer and method for producing thereof</title><author>Kabakow, Andre ; Rupp, Roland ; Konrath, Jens Peter ; Hecht, Christian</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11158557B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kabakow, Andre</creatorcontrib><creatorcontrib>Rupp, Roland</creatorcontrib><creatorcontrib>Konrath, Jens Peter</creatorcontrib><creatorcontrib>Hecht, Christian</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kabakow, Andre</au><au>Rupp, Roland</au><au>Konrath, Jens Peter</au><au>Hecht, Christian</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor device with a passivation layer and method for producing thereof</title><date>2021-10-26</date><risdate>2021</risdate><abstract>A semiconductor device includes a semiconductor body comprising a first surface and an edge surface, a contact electrode formed on the first surface and comprising an outer edge side, and a passivation layer section conformally covering the outer edge side of the contact electrode. The passivation layer section is a multi-layer stack comprising a first layer, a second layer, and a third layer. Each of the first, second and third layers comprise outer edge sides facing the edge surface and opposite facing inner edge sides. The outer edge side of the contact electrode is disposed laterally between the inner edge sides and the outer edge sides of each layer. The inner and outer edge sides of the third layer are closer to the outer edge side of the electrode than the respective inner and outer edge sides of the first and second layer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Semiconductor device with a passivation layer and method for producing thereof
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T20%3A53%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kabakow,%20Andre&rft.date=2021-10-26&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11158557B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true