Power semiconductor apparatus and manufacturing method therefor

Power semiconductor apparatus and manufacturing method therefor

A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9)...

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Hauptverfasser: Sakamoto, Ken, Shikano, Taketoshi, Kondo, Satoshi, Iwai, Takamasa, Kawashima, Hiroshi
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator Sakamoto, Ken
Shikano, Taketoshi
Kondo, Satoshi
Iwai, Takamasa
Kawashima, Hiroshi
description A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9). Sealing resin (1) seals the inner lead (5), the power die pad (7), the power semiconductor device (9), and the first metal thin line (11). The sealing resin (1) includes an insulating section (15) directly beneath the power die pad (7). A thickness of the insulating section (15) is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (1). A first hollow (14) is provided on an upper surface of the sealing resin (1) directly above the power die pad (7) in a region without the first metal thin line (11) and the power semiconductor device (9).
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11107746B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11107746B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11107746B23</originalsourceid><addsrcrecordid>eNqNyjEKQjEMANAuDqLeIR5AsCr-UVAUR0GdP6FN_R9sUtIUr-_iAZze8qbucJMPKVTKYxCOLZgoYCmoaK0CcoSM3BIGazryCzLZIBFsIKUkOneThO9Ki58zt7ycH6frior0VAsGYrL-effer7tutz9utv-cL__qMfQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Power semiconductor apparatus and manufacturing method therefor</title><source>esp@cenet</source><creator>Sakamoto, Ken ; Shikano, Taketoshi ; Kondo, Satoshi ; Iwai, Takamasa ; Kawashima, Hiroshi</creator><creatorcontrib>Sakamoto, Ken ; Shikano, Taketoshi ; Kondo, Satoshi ; Iwai, Takamasa ; Kawashima, Hiroshi</creatorcontrib><description>A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9). Sealing resin (1) seals the inner lead (5), the power die pad (7), the power semiconductor device (9), and the first metal thin line (11). The sealing resin (1) includes an insulating section (15) directly beneath the power die pad (7). A thickness of the insulating section (15) is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (1). A first hollow (14) is provided on an upper surface of the sealing resin (1) directly above the power die pad (7) in a region without the first metal thin line (11) and the power semiconductor device (9).</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210831&amp;DB=EPODOC&amp;CC=US&amp;NR=11107746B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210831&amp;DB=EPODOC&amp;CC=US&amp;NR=11107746B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Sakamoto, Ken</creatorcontrib><creatorcontrib>Shikano, Taketoshi</creatorcontrib><creatorcontrib>Kondo, Satoshi</creatorcontrib><creatorcontrib>Iwai, Takamasa</creatorcontrib><creatorcontrib>Kawashima, Hiroshi</creatorcontrib><title>Power semiconductor apparatus and manufacturing method therefor</title><description>A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9). Sealing resin (1) seals the inner lead (5), the power die pad (7), the power semiconductor device (9), and the first metal thin line (11). The sealing resin (1) includes an insulating section (15) directly beneath the power die pad (7). A thickness of the insulating section (15) is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (1). A first hollow (14) is provided on an upper surface of the sealing resin (1) directly above the power die pad (7) in a region without the first metal thin line (11) and the power semiconductor device (9).</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKQjEMANAuDqLeIR5AsCr-UVAUR0GdP6FN_R9sUtIUr-_iAZze8qbucJMPKVTKYxCOLZgoYCmoaK0CcoSM3BIGazryCzLZIBFsIKUkOneThO9Ki58zt7ycH6frior0VAsGYrL-effer7tutz9utv-cL__qMfQ</recordid><startdate>20210831</startdate><enddate>20210831</enddate><creator>Sakamoto, Ken</creator><creator>Shikano, Taketoshi</creator><creator>Kondo, Satoshi</creator><creator>Iwai, Takamasa</creator><creator>Kawashima, Hiroshi</creator><scope>EVB</scope></search><sort><creationdate>20210831</creationdate><title>Power semiconductor apparatus and manufacturing method therefor</title><author>Sakamoto, Ken ; Shikano, Taketoshi ; Kondo, Satoshi ; Iwai, Takamasa ; Kawashima, Hiroshi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11107746B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Sakamoto, Ken</creatorcontrib><creatorcontrib>Shikano, Taketoshi</creatorcontrib><creatorcontrib>Kondo, Satoshi</creatorcontrib><creatorcontrib>Iwai, Takamasa</creatorcontrib><creatorcontrib>Kawashima, Hiroshi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Sakamoto, Ken</au><au>Shikano, Taketoshi</au><au>Kondo, Satoshi</au><au>Iwai, Takamasa</au><au>Kawashima, Hiroshi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Power semiconductor apparatus and manufacturing method therefor</title><date>2021-08-31</date><risdate>2021</risdate><abstract>A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9). Sealing resin (1) seals the inner lead (5), the power die pad (7), the power semiconductor device (9), and the first metal thin line (11). The sealing resin (1) includes an insulating section (15) directly beneath the power die pad (7). A thickness of the insulating section (15) is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (1). A first hollow (14) is provided on an upper surface of the sealing resin (1) directly above the power die pad (7) in a region without the first metal thin line (11) and the power semiconductor device (9).</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Power semiconductor apparatus and manufacturing method therefor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-25T17%3A49%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Sakamoto,%20Ken&rft.date=2021-08-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11107746B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true