Integrated-circuitry overlay alignment mark, a substrate comprising an overlay alignment mark, a method of forming an overlay alignment mark in the fabrication of integrated circuitry, and a method of determining overlay alignment in the fabrication of integrated circuitry
A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the fi...
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creator | Housley, Richard T Zhou, Jianming Frost, Denzil S |
description | A method of forming an overlay alignment mark in the fabrication of integrated circuitry comprises forming a first series of periodically-horizontally-spaced lower first features on a substrate. A second series of periodically-horizontally-spaced upper second features is formed directly above the first series of the lower first features. Individual of the upper second features are directly above and cover at least a portion of individual of the lower first features in a first horizontal area of the substrate. Individual of the upper second features are not directly above and are not covering any portion of the individual lower first features in a second horizontal area of the substrate that is horizontally adjacent the first horizontal area. Other methods, and structure independent of method, are disclosed. |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Integrated-circuitry overlay alignment mark, a substrate comprising an overlay alignment mark, a method of forming an overlay alignment mark in the fabrication of integrated circuitry, and a method of determining overlay alignment in the fabrication of integrated circuitry |
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