Read from memory instructions, processors, methods, and systems, that do not take exception on defective data
A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in res...
Gespeichert in:
Hauptverfasser: | , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | Kumar, Mohan J Ghetie, Sergiu Raj, Ashok Jayakumar, Sarathy Upasani, Neeraj S Shafi, Hisham Gabor, Ron Yigzaw, Theodros |
description | A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11068339B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11068339B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11068339B23</originalsourceid><addsrcrecordid>eNqNjM0KwkAQg3vxIOo7jHcFtSB6VRTP_pzL0E1p0d1Zdkaxb-8KPoAQyBdIMiz8GeyoSeLJw0vqqQtq6VlbJ0FnFJPUUJWU2cNacRk4ONJeDT4Ha9nICQUxMr6D8K4Rv3PKcmiQv14gx8bjYtDwQzH5-aiYHg_X_WmOKBU0co0Aq26X5XKx3pTldrcq_-l8AFrPQhU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Read from memory instructions, processors, methods, and systems, that do not take exception on defective data</title><source>esp@cenet</source><creator>Kumar, Mohan J ; Ghetie, Sergiu ; Raj, Ashok ; Jayakumar, Sarathy ; Upasani, Neeraj S ; Shafi, Hisham ; Gabor, Ron ; Yigzaw, Theodros</creator><creatorcontrib>Kumar, Mohan J ; Ghetie, Sergiu ; Raj, Ashok ; Jayakumar, Sarathy ; Upasani, Neeraj S ; Shafi, Hisham ; Gabor, Ron ; Yigzaw, Theodros</creatorcontrib><description>A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210720&DB=EPODOC&CC=US&NR=11068339B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210720&DB=EPODOC&CC=US&NR=11068339B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kumar, Mohan J</creatorcontrib><creatorcontrib>Ghetie, Sergiu</creatorcontrib><creatorcontrib>Raj, Ashok</creatorcontrib><creatorcontrib>Jayakumar, Sarathy</creatorcontrib><creatorcontrib>Upasani, Neeraj S</creatorcontrib><creatorcontrib>Shafi, Hisham</creatorcontrib><creatorcontrib>Gabor, Ron</creatorcontrib><creatorcontrib>Yigzaw, Theodros</creatorcontrib><title>Read from memory instructions, processors, methods, and systems, that do not take exception on defective data</title><description>A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjM0KwkAQg3vxIOo7jHcFtSB6VRTP_pzL0E1p0d1Zdkaxb-8KPoAQyBdIMiz8GeyoSeLJw0vqqQtq6VlbJ0FnFJPUUJWU2cNacRk4ONJeDT4Ha9nICQUxMr6D8K4Rv3PKcmiQv14gx8bjYtDwQzH5-aiYHg_X_WmOKBU0co0Aq26X5XKx3pTldrcq_-l8AFrPQhU</recordid><startdate>20210720</startdate><enddate>20210720</enddate><creator>Kumar, Mohan J</creator><creator>Ghetie, Sergiu</creator><creator>Raj, Ashok</creator><creator>Jayakumar, Sarathy</creator><creator>Upasani, Neeraj S</creator><creator>Shafi, Hisham</creator><creator>Gabor, Ron</creator><creator>Yigzaw, Theodros</creator><scope>EVB</scope></search><sort><creationdate>20210720</creationdate><title>Read from memory instructions, processors, methods, and systems, that do not take exception on defective data</title><author>Kumar, Mohan J ; Ghetie, Sergiu ; Raj, Ashok ; Jayakumar, Sarathy ; Upasani, Neeraj S ; Shafi, Hisham ; Gabor, Ron ; Yigzaw, Theodros</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11068339B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Kumar, Mohan J</creatorcontrib><creatorcontrib>Ghetie, Sergiu</creatorcontrib><creatorcontrib>Raj, Ashok</creatorcontrib><creatorcontrib>Jayakumar, Sarathy</creatorcontrib><creatorcontrib>Upasani, Neeraj S</creatorcontrib><creatorcontrib>Shafi, Hisham</creatorcontrib><creatorcontrib>Gabor, Ron</creatorcontrib><creatorcontrib>Yigzaw, Theodros</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kumar, Mohan J</au><au>Ghetie, Sergiu</au><au>Raj, Ashok</au><au>Jayakumar, Sarathy</au><au>Upasani, Neeraj S</au><au>Shafi, Hisham</au><au>Gabor, Ron</au><au>Yigzaw, Theodros</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Read from memory instructions, processors, methods, and systems, that do not take exception on defective data</title><date>2021-07-20</date><risdate>2021</risdate><abstract>A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US11068339B2 |
source | esp@cenet |
subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Read from memory instructions, processors, methods, and systems, that do not take exception on defective data |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T13%3A05%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kumar,%20Mohan%20J&rft.date=2021-07-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11068339B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |