Branch target buffer with early return prediction

A processor includes a branch target buffer (BTB) having a plurality of entries whereby each entry corresponds to an associated instruction pointer value that is predicted to be a branch instruction. Each BTB entry stores a predicted branch target address for the branch instruction, and further stor...

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Bibliographische Detailangaben
Hauptverfasser: Evers, Marius, Annamalai, Arunachalam, Thyagarajan, Aparna
Format: Patent
Sprache:eng
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