Cache storage for multiple requesters and usage estimation thereof
A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the p...
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creator | Ramrakhyani, Prakash S Saidi, Ali |
description | A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11030101B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11030101B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11030101B23</originalsourceid><addsrcrecordid>eNqNykEKwjAQRuFsXIh6h_EAQmJv0KK4V9dlqH9sIE1iZnJ_FTyAqwePb236gacZJJorP0E-V1pa1FAiqOLVIIoqxOlBTb7iM8LCGnIinVGR_dasPEfB7teN2Z9Pt-FyQMkjpPCEBB3vV-dsZ511_bH7x7wBZLUybA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Cache storage for multiple requesters and usage estimation thereof</title><source>esp@cenet</source><creator>Ramrakhyani, Prakash S ; Saidi, Ali</creator><creatorcontrib>Ramrakhyani, Prakash S ; Saidi, Ali</creatorcontrib><description>A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210608&DB=EPODOC&CC=US&NR=11030101B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210608&DB=EPODOC&CC=US&NR=11030101B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ramrakhyani, Prakash S</creatorcontrib><creatorcontrib>Saidi, Ali</creatorcontrib><title>Cache storage for multiple requesters and usage estimation thereof</title><description>A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNykEKwjAQRuFsXIh6h_EAQmJv0KK4V9dlqH9sIE1iZnJ_FTyAqwePb236gacZJJorP0E-V1pa1FAiqOLVIIoqxOlBTb7iM8LCGnIinVGR_dasPEfB7teN2Z9Pt-FyQMkjpPCEBB3vV-dsZ511_bH7x7wBZLUybA</recordid><startdate>20210608</startdate><enddate>20210608</enddate><creator>Ramrakhyani, Prakash S</creator><creator>Saidi, Ali</creator><scope>EVB</scope></search><sort><creationdate>20210608</creationdate><title>Cache storage for multiple requesters and usage estimation thereof</title><author>Ramrakhyani, Prakash S ; Saidi, Ali</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11030101B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Ramrakhyani, Prakash S</creatorcontrib><creatorcontrib>Saidi, Ali</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ramrakhyani, Prakash S</au><au>Saidi, Ali</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cache storage for multiple requesters and usage estimation thereof</title><date>2021-06-08</date><risdate>2021</risdate><abstract>A cache memory and method of operating a cache memory are provided. The cache memory comprises cache storage that stores cache lines for a plurality of requesters and cache control circuitry that controls insertion of a cache line into the cache storage when a memory access request from one of the plurality of requesters misses in the cache memory. The cache memory further has cache occupancy estimation circuitry that holds a count of insertions of cache lines into the cache storage for each of the plurality of requesters over a defined period. The count of cache line insertions for each requester thus provides an estimation of the cache occupancy associated with each requester.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | Cache storage for multiple requesters and usage estimation thereof |
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