Failure detection apparatus, failure detection method, and non-transitory computer readable recording medium

A failure detection apparatus (10) includes a RAM (125) and a controller (122) configured to execute processing related to detection of a physical quantity in a predetermined sampling period (T1). The RAM (125) includes partitioned areas generated by partitioning the entire area of the RAM (125). Th...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Tanaka, Hidekazu, Igarashi, Shouji, Kajikawa, Tomohiro
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Tanaka, Hidekazu Igarashi, Shouji Kajikawa, Tomohiro
description	A failure detection apparatus (10) includes a RAM (125) and a controller (122) configured to execute processing related to detection of a physical quantity in a predetermined sampling period (T1). The RAM (125) includes partitioned areas generated by partitioning the entire area of the RAM (125). The controller (122) is configured to execute sequential failure detection on a portion of the partitioned areas during a time when the controller (122) is not executing the processing in each of the sampling periods (T1).
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11030028B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11030028B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11030028B23</originalsourceid><addsrcrecordid>eNqNi7sOwjAMRbswIOAfzN5KfSzMICp2YK5M4kKkJI4cZ-Dv6cDGwnSPdM5dV35E54sQWFIy6jgCpoSCWnIN848MpC-2NWC0EDk2KhizU5Y3GA6pKAkIocWHpwUMi3XxudysK2FbrWb0mXbf3VT78Xw7XRpKPFFOaCiSTvdr17VD2_aHYz_803wAe0ZChA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Failure detection apparatus, failure detection method, and non-transitory computer readable recording medium</title><source>esp@cenet</source><creator>Tanaka, Hidekazu ; Igarashi, Shouji ; Kajikawa, Tomohiro</creator><creatorcontrib>Tanaka, Hidekazu ; Igarashi, Shouji ; Kajikawa, Tomohiro</creatorcontrib><description>A failure detection apparatus (10) includes a RAM (125) and a controller (122) configured to execute processing related to detection of a physical quantity in a predetermined sampling period (T1). The RAM (125) includes partitioned areas generated by partitioning the entire area of the RAM (125). The controller (122) is configured to execute sequential failure detection on a portion of the partitioned areas during a time when the controller (122) is not executing the processing in each of the sampling periods (T1).</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210608&DB=EPODOC&CC=US&NR=11030028B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25568,76551</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210608&DB=EPODOC&CC=US&NR=11030028B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tanaka, Hidekazu</creatorcontrib><creatorcontrib>Igarashi, Shouji</creatorcontrib><creatorcontrib>Kajikawa, Tomohiro</creatorcontrib><title>Failure detection apparatus, failure detection method, and non-transitory computer readable recording medium</title><description>A failure detection apparatus (10) includes a RAM (125) and a controller (122) configured to execute processing related to detection of a physical quantity in a predetermined sampling period (T1). The RAM (125) includes partitioned areas generated by partitioning the entire area of the RAM (125). The controller (122) is configured to execute sequential failure detection on a portion of the partitioned areas during a time when the controller (122) is not executing the processing in each of the sampling periods (T1).</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi7sOwjAMRbswIOAfzN5KfSzMICp2YK5M4kKkJI4cZ-Dv6cDGwnSPdM5dV35E54sQWFIy6jgCpoSCWnIN848MpC-2NWC0EDk2KhizU5Y3GA6pKAkIocWHpwUMi3XxudysK2FbrWb0mXbf3VT78Xw7XRpKPFFOaCiSTvdr17VD2_aHYz_803wAe0ZChA</recordid><startdate>20210608</startdate><enddate>20210608</enddate><creator>Tanaka, Hidekazu</creator><creator>Igarashi, Shouji</creator><creator>Kajikawa, Tomohiro</creator><scope>EVB</scope></search><sort><creationdate>20210608</creationdate><title>Failure detection apparatus, failure detection method, and non-transitory computer readable recording medium</title><author>Tanaka, Hidekazu ; Igarashi, Shouji ; Kajikawa, Tomohiro</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11030028B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Tanaka, Hidekazu</creatorcontrib><creatorcontrib>Igarashi, Shouji</creatorcontrib><creatorcontrib>Kajikawa, Tomohiro</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tanaka, Hidekazu</au><au>Igarashi, Shouji</au><au>Kajikawa, Tomohiro</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Failure detection apparatus, failure detection method, and non-transitory computer readable recording medium</title><date>2021-06-08</date><risdate>2021</risdate><abstract>A failure detection apparatus (10) includes a RAM (125) and a controller (122) configured to execute processing related to detection of a physical quantity in a predetermined sampling period (T1). The RAM (125) includes partitioned areas generated by partitioning the entire area of the RAM (125). The controller (122) is configured to execute sequential failure detection on a portion of the partitioned areas during a time when the controller (122) is not executing the processing in each of the sampling periods (T1).</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US11030028B2
source	esp@cenet
subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	Failure detection apparatus, failure detection method, and non-transitory computer readable recording medium
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T09%3A28%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tanaka,%20Hidekazu&rft.date=2021-06-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11030028B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true