Vertical fin field effect transistor with air gap spacers
A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between th...
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creator | Robison, Robert R Vega, Reinaldo A Mallela, Hari V Venigalla, Rajasekhar |
description | A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill. |
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ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210601&DB=EPODOC&CC=US&NR=11024709B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210601&DB=EPODOC&CC=US&NR=11024709B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Robison, Robert R</creatorcontrib><creatorcontrib>Vega, Reinaldo A</creatorcontrib><creatorcontrib>Mallela, Hari V</creatorcontrib><creatorcontrib>Venigalla, Rajasekhar</creatorcontrib><title>Vertical fin field effect transistor with air gap spacers</title><description>A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAMSy0qyUxOzFFIy8wD4tScFIXUtLTU5BKFkqLEvOLM4pL8IoXyzJIMhcTMIoX0xAKF4oLE5NSiYh4G1rTEnOJUXijNzaDo5hri7KGbWpAfnwpWlJdaEh8abGhoYGRibmDpZGRMjBoAMYYupg</recordid><startdate>20210601</startdate><enddate>20210601</enddate><creator>Robison, Robert R</creator><creator>Vega, Reinaldo A</creator><creator>Mallela, Hari V</creator><creator>Venigalla, Rajasekhar</creator><scope>EVB</scope></search><sort><creationdate>20210601</creationdate><title>Vertical fin field effect transistor with air gap spacers</title><author>Robison, Robert R ; Vega, Reinaldo A ; Mallela, Hari V ; Venigalla, Rajasekhar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11024709B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Robison, Robert R</creatorcontrib><creatorcontrib>Vega, Reinaldo A</creatorcontrib><creatorcontrib>Mallela, Hari V</creatorcontrib><creatorcontrib>Venigalla, Rajasekhar</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Robison, Robert R</au><au>Vega, Reinaldo A</au><au>Mallela, Hari V</au><au>Venigalla, Rajasekhar</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Vertical fin field effect transistor with air gap spacers</title><date>2021-06-01</date><risdate>2021</risdate><abstract>A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Vertical fin field effect transistor with air gap spacers |
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