Memory circuit layout method
A method includes placing first and second oxide diffusion (OD) layout patterns in a layout design corresponding to first, second, third, and fourth memory cells of a memory circuit. The first OD layout pattern extends along a first direction and has a first source portion shared between the first a...
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| creator | Chang, Jacklyn Hsu, Kuoyuan (Peter) |
| description | A method includes placing first and second oxide diffusion (OD) layout patterns in a layout design corresponding to first, second, third, and fourth memory cells of a memory circuit. The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. The method is wholly or partially performed by using a hardware processor. |
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The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. 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The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. 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The first OD layout pattern extends along a first direction and has a first source portion shared between the first and second memory cells, and the second OD layout pattern extends along the first direction and has a second source portion shared between the third and fourth memory cells. The method includes placing a first conductive layout pattern in the layout diagram, the first conductive layout pattern corresponding to a first conductive structure under a lowest via plug layer of the memory circuit, extending along a second direction, and overlapping the first source portion and the second source portion. The method is wholly or partially performed by using a hardware processor.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES |
| title | Memory circuit layout method |
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