Latency-based instruction reservation station clustering in a scheduler circuit in a processor

Latency-based instruction reservation clustering in a scheduler circuit in a processor is disclosed. The scheduler circuit includes a plurality of latency-based reservation circuits each having an assigned producer instruction cycle latency. Producer instructions with the same cycle latency can be c...

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Bibliographische Detailangaben

Hauptverfasser:	Tekmen, Yusuf Cagatay, Priyadarshi, Shivam, Smith, Rodney Wayne
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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