Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit

An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Shin, Seong-kyun, Kwak, Myoung-bo, Choi, Jung-myung, Lee, Dae-wung, Shin, Jong-shin, Burm, Jin-wook, Yu, Chang-zhi
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Shin, Seong-kyun
Kwak, Myoung-bo
Choi, Jung-myung
Lee, Dae-wung
Shin, Jong-shin
Burm, Jin-wook
Yu, Chang-zhi
description An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US11012077B2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US11012077B2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US11012077B23</originalsourceid><addsrcrecordid>eNqNTTsOgkAUpLEw6h2eBzABLOg1Gq3Vmry8HXDjZsHdhwkH8N6KGgsrq_lmZpzc915RB1YYEhuks0oGClHra6oCrh289MTeUHvmCGoqEtfIhaKtPbtX8jYGZliZAqS5IfTfRevFdWZY1DOe6vdymowqdhGzD06S-XZzXO8WaJsSsWWBh5anQ5alWZ4WxSpf_tN5APXpS3I</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit</title><source>esp@cenet</source><creator>Shin, Seong-kyun ; Kwak, Myoung-bo ; Choi, Jung-myung ; Lee, Dae-wung ; Shin, Jong-shin ; Burm, Jin-wook ; Yu, Chang-zhi</creator><creatorcontrib>Shin, Seong-kyun ; Kwak, Myoung-bo ; Choi, Jung-myung ; Lee, Dae-wung ; Shin, Jong-shin ; Burm, Jin-wook ; Yu, Chang-zhi</creatorcontrib><description>An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210518&amp;DB=EPODOC&amp;CC=US&amp;NR=11012077B2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210518&amp;DB=EPODOC&amp;CC=US&amp;NR=11012077B2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Shin, Seong-kyun</creatorcontrib><creatorcontrib>Kwak, Myoung-bo</creatorcontrib><creatorcontrib>Choi, Jung-myung</creatorcontrib><creatorcontrib>Lee, Dae-wung</creatorcontrib><creatorcontrib>Shin, Jong-shin</creatorcontrib><creatorcontrib>Burm, Jin-wook</creatorcontrib><creatorcontrib>Yu, Chang-zhi</creatorcontrib><title>Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit</title><description>An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNTTsOgkAUpLEw6h2eBzABLOg1Gq3Vmry8HXDjZsHdhwkH8N6KGgsrq_lmZpzc915RB1YYEhuks0oGClHra6oCrh289MTeUHvmCGoqEtfIhaKtPbtX8jYGZliZAqS5IfTfRevFdWZY1DOe6vdymowqdhGzD06S-XZzXO8WaJsSsWWBh5anQ5alWZ4WxSpf_tN5APXpS3I</recordid><startdate>20210518</startdate><enddate>20210518</enddate><creator>Shin, Seong-kyun</creator><creator>Kwak, Myoung-bo</creator><creator>Choi, Jung-myung</creator><creator>Lee, Dae-wung</creator><creator>Shin, Jong-shin</creator><creator>Burm, Jin-wook</creator><creator>Yu, Chang-zhi</creator><scope>EVB</scope></search><sort><creationdate>20210518</creationdate><title>Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit</title><author>Shin, Seong-kyun ; Kwak, Myoung-bo ; Choi, Jung-myung ; Lee, Dae-wung ; Shin, Jong-shin ; Burm, Jin-wook ; Yu, Chang-zhi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US11012077B23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Shin, Seong-kyun</creatorcontrib><creatorcontrib>Kwak, Myoung-bo</creatorcontrib><creatorcontrib>Choi, Jung-myung</creatorcontrib><creatorcontrib>Lee, Dae-wung</creatorcontrib><creatorcontrib>Shin, Jong-shin</creatorcontrib><creatorcontrib>Burm, Jin-wook</creatorcontrib><creatorcontrib>Yu, Chang-zhi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shin, Seong-kyun</au><au>Kwak, Myoung-bo</au><au>Choi, Jung-myung</au><au>Lee, Dae-wung</au><au>Shin, Jong-shin</au><au>Burm, Jin-wook</au><au>Yu, Chang-zhi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit</title><date>2021-05-18</date><risdate>2021</risdate><abstract>An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US11012077B2
source esp@cenet
subjects AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-04T07%3A11%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Shin,%20Seong-kyun&rft.date=2021-05-18&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS11012077B2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true