Fault detection and localization to generate failing test cases using combinatorial test design techniques

Systems, methods, and computer-readable media are described for performing fault detection and localization using Combinatorial Test Design (CTD) techniques and generating a regression bucket of test cases that expose a detected fault in a System Under Test (SUT). The SUT may be a hardware system or...

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Hauptverfasser:	Rawlins, Ryan, Blue, Dale E, Brill, Rachel, Hicks, Andrew
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Rawlins, Ryan Blue, Dale E Brill, Rachel Hicks, Andrew
description	Systems, methods, and computer-readable media are described for performing fault detection and localization using Combinatorial Test Design (CTD) techniques and generating a regression bucket of test cases that expose a detected fault in a System Under Test (SUT). The SUT may be a hardware system or a software system. Further, the fault detection and localization may be performed while adhering to architectural restrictions on the SUT.
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title	Fault detection and localization to generate failing test cases using combinatorial test design techniques
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